Doctoral Training Network for Design of Resilient Systems-on-Chip
Reliable electronics is essential in safety- and mission-critical domains, such as space missions, aviation, automotive, wireless communications, data centers, healthcare, automated industry. With increase in complexity of Integrated Circuit (ICs), advancement in semiconductor technology and evolving market trends and application requirements, the IC design paradigm is shifting from classic “reliable systems” to “resilient systems”. A resilient IC has the ability to monitor its own state, detect and predict faulty scanarios, and perform self-reconfiguration/self-healing to maintain the required functionality. Besides ensuring enhanced reliability and safety, resilient systems aim to provide a balance between performance, fault tolerance and power consumption, resulting in extended system lifetime. Given the strategic goal of EU to enhance its capacities in semiconductor domain (European Chips Act), as well as the shortage of highly skilled personnel for IC design, there is an urgent need for creating a new generation of skilled experts for ICs design. As the demand for safety- and mission-critical applications is projected to increase in coming years, particularly with new space missions and adoption of 6G wireless communications across numerous domains, special attention should be given to boosting the European capacities in the design of resilient Systems-on-Chip (SoC). The RESYST-CHIP project will train 15 highly-skilled and entrepreneurially-oriented researchers in the design of resilient SoCs. The project brings together 20 leading research institutes, universities and companies, with the aim to address synergistically the critical challenges in 4 research domains - reliability characterization and modeling, CAD tools for resilience-by-design, on-chip sensing and analytics, and design of resilient architectures. The RESYST-CHIP network will employ a comprehensive training program combining complementary scientific and transferrable skills training.
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Imported from OpenAIRE United Kingdom | Grant 101312702.
Open sourceOverview
Grant agreement 101312702 | RESYST-CHIP
Open sourceReliable electronics is essential in safety- and mission-critical domains, such as space missions, aviation, automotive, wireless communications, data centers, healthcare, automated industry. With increase in complexity of Integrated Circuit (ICs), advancement in semiconductor technology and evolving market trends and application requirements, the IC design paradigm is shifting from classic “reliable systems” to “resilient systems”. A resilient IC has the ability to monitor its own state, detect and predict faulty scanarios, and perform self-reconfiguration/self-healing to maintain the required functionality. Besides ensuring enhanced reliability and safety, resilient systems aim to provide a balance between performance, fault tolerance and power consumption, resulting in extended system lifetime. Given the strategic goal of EU to enhance its capacities in semiconductor domain (European Chips Act), as well as the shortage of highly skilled personnel for IC design, there is an urgent need for creating a new generation of skilled experts for ICs design. As the demand for safety- and mission-critical applications is projected to increase in coming years, particularly with new space missions and adoption of 6G wireless communications across numerous domains, special attention should be given to boosting the European capacities in the design of resilient Systems-on-Chip (SoC). The RESYST-CHIP project will train 15 highly-skilled and entrepreneurially-oriented researchers in the design of resilient SoCs. The project brings together 20 leading research institutes, universities and companies, with the aim to address synergistically the critical challenges in 4 research domains - reliability characterization and modeling, CAD tools for resilience-by-design, on-chip sensing and analytics, and design of resilient architectures. The RESYST-CHIP network will employ a comprehensive training program combining complementary scientific and transferrable skills training.